Back to VLSI Design (CMCE & CCEE)
01

SystemVerilog for Design and Verification

40 MCQs•60 Mins•40 Marks•No Negative Marking
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02

Advanced Verification using UVM

40 MCQs•60 Mins•40 Marks•No Negative Marking
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03

CMOS VLSI and Aspects of ASIC Design

40 MCQs•60 Mins•40 Marks•No Negative Marking
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04

Physical Design & Static Timing Analysis

40 MCQs•60 Mins•40 Marks•No Negative Marking
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